1. Field of the Invention
Embodiments of the present invention relate to a flash memory card including an integrated circuit package having test pads.
2. Description of the Related Art
As the sizes of electronic devices continue to decrease, the associated semiconductor packages that operate them are being designed with smaller form factors, lower power requirements and higher functionality. Currently, sub-micron features in semiconductor fabrication are placing higher demands on package technology including higher lead counts, reduced lead pitch, minimum footprint area and significant overall volume reduction.
One branch of semiconductor packaging involves the use of a leadframe, which is a thin layer of metal on which one or more semiconductor die are mounted and supported. The leadframe includes electrical leads for communicating electrical signals from the one or more semiconductors to a printed circuit board or other external electrical devices. FIG. 1 shows a leadframe 20 before attachment of a semiconductor die 22. A typical leadframe 20 may include a number of leads 24 having first ends 24a for attaching to semiconductor die 22, and a second end (not shown) for affixing to a printed circuit board or other electrical component. Leadframe 20 may further include a die attach pad 26 for structurally supporting semiconductor die 22 on leadframe 20. While die attach pad 26 may provide a path to ground, it conventionally does not carry signals to or from the semiconductor die 22. In certain leadframe configurations, it is known to omit die attach pad 26 and instead attach the semiconductor die directly to the leadframe leads in a so-called chip on lead (COL) configuration.
Semiconductor leads 24 may be mounted to die attach pad 26 as shown in FIG. 2 using a die attach compound. Semiconductor die 22 is conventionally formed with a plurality of die bond pads 28 on at least first and second opposed edges on the top side of the semiconductor die. Once the semiconductor die is mounted to the leadframe, a wire bond process is performed whereby bond pads 28 are electrically coupled to respective electrical leads 24 using a delicate wire 30. The assignment of a bond pad 28 to a particular electrical lead 24 is defined by industry standard specification. FIG. 2 shows less than all of the bond pads 28 being wired to leads 24 for clarity, but each bond pad may be wired to its respective electrical lead in conventional designs. It is also known to have less than all of the bond pads wired to an electrical lead as shown in FIG. 2.
Typically, leadframe 20 is initially formed from a panel including a plurality of such leadframes. The semiconductor die 22 are mounted and electrically connected to each leadframe in the panel, and the integrated circuits formed thereby are encapsulated in a molding compound. Thereafter, the individual encapsulated integrated circuits are cut from the panel, or singulated, into a plurality of semiconductor packages.
It is known to form test pads within the semiconductor package. The test pads typically are exposed to the outside of the package and are electrically connected internally to one or more of the semiconductor die in the package. After fabrication of a semiconductor package, the package may be inserted into a socket on a test card, whereupon the test pads are contacted by probes to test the electrical properties and functioning of the semiconductor package to determine whether the finished semiconductor package performs per specification.
Typically, a pattern for the test pads is formed in a leadframe or other substrate such as a printed circuit board during the substrate fabrication step. The pattern may for example be formed in a chemical etching or mechanical stamping process. After formation, the test pads are left exposed during the molding encapsulation step in forming the package to allow access to the test pads after package formation. Once the package is fabricated and tested via the test pads, the package may be encased in a pair of mating lids which cover the test pads, and prevent their access while the semiconductor package is in use.